• DocumentCode
    3251452
  • Title

    Power comparison of low bitwidth multipliers

  • Author

    Hildebrandt, Ralf

  • Author_Institution
    Fraunhofer IPMS, Dresden, Germany
  • fYear
    2004
  • fDate
    6-8 Dec. 2004
  • Firstpage
    162
  • Lastpage
    165
  • Abstract
    Some common and new low bitwidth signed-digit, carry-save and carry-ribble multipliers are compared at point of view of power dissipation at gate level. Results of synthesis and power simulation with an analog simulator are presented. SD multipliers are relatively big, slow and very power-consuming like expected. From the point of view of the synthesized netlist SD multipliers are not suitable as a replacement of CS multipliers. However, routing of SD-trees is simpler than routing of a Wallace-tree because of the 2 to 1 reduction.
  • Keywords
    adders; analogue simulation; carry logic; multiplying circuits; analog simulator; carry ribble multiplier; carry save multiplier; low bitwidth signed digit multiplier; power dissipation; power simulation; signed digit trees; Acceleration; Adders; Circuits; Computational modeling; Delay estimation; Encoding; Gold; Hardware; Power dissipation; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microelectronics, 2004. ICM 2004 Proceedings. The 16th International Conference on
  • Print_ISBN
    0-7803-8656-6
  • Type

    conf

  • DOI
    10.1109/ICM.2004.1434234
  • Filename
    1434234