Case study : Co-simulation and co-emulation environments based on SystemC & SystemVerilog

The flow of universal system-level design methodology consists of system specification, system-level hardware/software partitioning, co-design, co-verification using virtual or physical prototype, and system integration. In this paper, hardware part and software part of a design are described with SystemVerilog and SystemC, respectively after hardware/software partitioning. The functional interaction between hardware part and software part of a design is verified through co-simulation in pure software domain, and then verified through co-emulation after implementation of hardware part onto a specific hardware emulator. Verilog PLI provides a mechanism for Verilog simulators to invoke C functions which are registered as system functions through a complex process of library registration. Communication between software part and hardware part running concurrently needs IPC. Low-level system functions of device driver or kernel are called from C functions which are registered into Verilog PLI library. In contrast to Verilog PLI, SystemVerilog DPI which is used in co-simulation of this paper provides a way to interface with C/C++ or any other foreign language. Functions and tasks registered to the shared library using DPI can be called out like native ones. ModelSim recently supports SystemC simulation with built-in compiler for SystemC design unit, so the co-simulation of SystemC design units and SystemVerilog modules is carried out as one simulation process on ModelSim. After co-simulation, co-emulation using an FPGA-based prototype board is carried out.