A self-aligned split-gate flash EEPROM cell with 3-D pillar structure

Author

Hayashi, F. ; Plummer, J.D.

Author_Institution

Center for Integrated Syst., Stanford Univ., CA, USA

fYear

1999

fDate

14-16 June 1999

Firstpage

87

Lastpage

88

Abstract

A novel 3D memory cell has been proposed for high density future generation flash EEPROMs. A self-aligned split-gate (SASG) structure, minimizing the split-gate length, has been implemented in a pillar-shape cell with high scalability over the tunnel oxide scaling limitation. This cell technology allows an ideal split-gate cell size of 6F/sup 2/. Good programming and erase characteristics have been obtained and over-erasing has been suppressed down to a 0.1 /spl mu/m split-gate length in experimental devices.

Keywords

PLD programming; dielectric thin films; flash memories; integrated circuit testing; integrated memory circuits; microprogramming; 0.1 micron; 3D memory cell; 3D pillar structure; SASG structure; SiO/sub 2/-Si; cell technology; flash EEPROMs; high density flash EEPROMs; over-erasing suppression; pillar-shape cell; programming/erase characteristics; scalability; self-aligned split-gate flash EEPROM cell; self-aligned split-gate structure; split-gate cell size; split-gate length minimization; tunnel oxide scaling limitation; EPROM; Etching; Flash memory; Leakage current; Metalworking machines; Nonvolatile memory; Scalability; Silicon; Split gate flash memory cells; Thickness control;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-930813-93-X

Type

conf

DOI

10.1109/VLSIT.1999.799353

Filename

799353