65 nm physical gate length NMOSFETs with heavy ion implanted pockets and highly reliable 2 nm-thick gate oxide for 1.5 V operation

Author

Caillat, C. ; Deleonibus, S. ; Guegan, G. ; Tedesco, S. ; Dal´zotto, B. ; Heitzmann, M. ; Martin, F. ; Mur, P. ; Marchand, B. ; Balestra, F.

Author_Institution

LETI, CEA, Centre d´Etudes Nucleaires de Grenoble, France

fYear

1999

fDate

14-16 June 1999

Firstpage

89

Lastpage

90

Abstract

For the first time, 65 nm physical gate length NMOS devices combining heavy ion (gallium, indium) implanted pockets and low leakage, highly reliable 2 nm-thick gate oxide are reported. Indium pockets allow us to obtain 0.33 V threshold voltage, low off-state leakage current (<6/spl times/10/sup -7/ A//spl mu/m) devices, usable for 1.5 V operation. The weak influence of pockets on NMOSFET reliability is demonstrated: extrapolated lifetime of 65 nm indium pocket devices at 1.65 V drain bias exceeds 27 years, which is consistent with 1.5 V operation.

Keywords

CMOS integrated circuits; MOSFET; dielectric thin films; doping profiles; extrapolation; ion implantation; leakage currents; semiconductor device reliability; 0.33 V; 1.5 V; 1.65 V; 2 nm; 27 yr; 65 nm; NMOS devices; NMOSFET reliability; NMOSFETs; Si:Ga; Si:In; drain bias; extrapolated lifetime; gallium ion implanted pockets; gate oxide; heavy ion implanted pockets; high reliability gate oxide; indium ion implanted pockets; indium pocket devices; off-state leakage current; physical gate length; threshold voltage; Capacitance; Gallium compounds; III-V semiconductor materials; Implants; Indium; Leakage current; MOS devices; MOSFETs; Semiconductor device reliability; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-930813-93-X

Type

conf

DOI

10.1109/VLSIT.1999.799354

Filename

799354