Inner cylinder Ta/sub 2/O/sub 5/ capacitor process for 1 Gb DRAM and beyond

Author

Seok Jun Won ; Yong Woo Hyung ; Kab Jin Nam ; Young Dae Kim ; Ki Yeon Park ; Young Wook Park ; Sang In Lee ; Moon Young Lee

Author_Institution

Semicond. R&D Center, Samsung Electron. Co. Ltd., Yongin-City, South Korea

fYear

1999

fDate

14-16 June 1999

Firstpage

97

Lastpage

98

Abstract

Capacitor manufacturing technology for 0.13 /spl mu/m design rule 1 Gbit DRAMs has been developed using an improved MIS (metal-insulator-semiconductor) tantalum oxide capacitor module process in a cylinder-shaped storage node with rugged-type inner surface (called inner cylinder). Capacitance of more than 26 fF/cell, leakage current of below 0.2 fA/cell at V/sub p/=1.0 V and breakdown lifetime of over 10 years were obtained as electrical properties, satisfying production level requirements.

Keywords

DRAM chips; MIS capacitors; capacitance; electrolytic capacitors; integrated circuit design; integrated circuit measurement; leakage currents; semiconductor device breakdown; tantalum compounds; 0.13 micron; 1 Gbit; 1 V; 10 yr; DRAM; MIS tantalum oxide capacitor module process; Ta/sub 2/O/sub 5/; breakdown lifetime; capacitor manufacturing technology; cell capacitance; cylinder-shaped storage node; design rule; electrical properties; inner cylinder; inner cylinder Ta/sub 2/O/sub 5/ capacitor process; leakage current; metal-insulator-semiconductor tantalum oxide capacitor module process; production level requirements; rugged-type inner surface; Annealing; Breakdown voltage; Capacitors; Curing; Dielectric measurements; Paper technology; Random access memory; Sorting; Testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-930813-93-X

Type

conf

DOI

10.1109/VLSIT.1999.799358

Filename

799358