DocumentCode
3251786
Title
Realization of 0.1 /spl mu/m buried-channel PMOSFETs by device restructuring using tilted well implantation technology
Author
Tanaka, T. ; Momiyama, Y. ; Goto, K. ; Sambonsugi, Y. ; Deura, M. ; Sugii, T.
Author_Institution
Fujitsu Labs. Ltd., Atsugi, Japan
fYear
1999
fDate
14-16 June 1999
Firstpage
109
Lastpage
110
Abstract
Device restructuring by tilted well implantation (TWI) was proposed for highly cost effective system LSIs. We demonstrated a 0.1 /spl mu/m buried-channel (BC) PMOSFET with a superior I/sub on//I/sub off/ ratio, little threshold voltage (V/sub th/) roll-off, and a low V/sub th/ using the TWI.
Keywords
CMOS integrated circuits; MOSFET; buried layers; electric current; ion implantation; semiconductor device measurement; 0.1 micron; buried-channel PMOSFET; buried-channel PMOSFETs; cost effective system LSIs; current on/off ratio; device restructuring; threshold voltage roll-off; threshold voltage swing; tilted well implantation technology; Boron; Circuits; Costs; Impurities; Laboratories; Length measurement; MOSFETs; Oxidation; Random access memory; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
4-930813-93-X
Type
conf
DOI
10.1109/VLSIT.1999.799364
Filename
799364
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