Integration of 3 level air gap interconnect for sub-quarter micron CMOS

Author

Ueda, T. ; Yamashita, K. ; Tamaoka, E. ; Sato, H. ; Egashira, K. ; Aoi, N. ; Ogura, M.

Author_Institution

ULSI Process Technol. Dev. Center, Matsushita Electron. Corp., Kyoto, Japan

fYear

1999

fDate

14-16 June 1999

Firstpage

111

Lastpage

112

Abstract

A three-level interconnect structure using an air gap process has been successfully fabricated. The practical use of air gap interconnects has been proved by evaluating via chain yield and EM properties. The RC delay time is reduced by 38% as compared with that of Al-SiOF. The circuit performance has been found to be superior to those of other low-k interconnects, including Cu-SiOF. This air gap process is quite promising for sub-0.25 /spl mu/m CMOS technology.

Keywords

CMOS integrated circuits; ULSI; air gaps; delays; integrated circuit interconnections; integrated circuit measurement; integrated circuit metallisation; integrated circuit reliability; integrated circuit yield; permittivity; 0.25 micron; Al-SiOF; Al-SiOF structure; CMOS technology; Cu-SiOF; Cu-SiOF structure; EM properties; RC delay time; air gap interconnects; air gap process; circuit performance; low-k interconnects; three-level air gap interconnect integration; three-level interconnect structure; via chain yield; Artificial intelligence; CMOS technology; Capacitance; Delay effects; Dielectric materials; Integrated circuit interconnections; Power dissipation; Temperature; Ultra large scale integration; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-930813-93-X

Type

conf

DOI

10.1109/VLSIT.1999.799365

Filename

799365