R-2 gate insulator;Hi-k vs. SiO/sub 2/

Summary form only given. The International Technology Roadmap for Semiconductors (ITRS) has monitored the evolution of the gate dielectric equivalent oxide thickness with technology node. The advent of ultra-thin dielectrics (51.5 nm equivalent oxide thickness)has exacerbated the measurement metrology, MOSFET off-state leakage and component reliability. These issues may be partially addressed by the utilization of single or multi-layer oxynitride stacks, eventually in conjunction with metal electrodes, although it is expected that the sub 70 nm node will be especially critical. In that regard, the possible utilization of high K gate dielectrics (and its relevant metal electrodes) is being explored as a possible solution.