A reliable 0.1 /spl mu/m Ta/sub 2/O/sub 5/ transistor manufactured with an almost standard CMOS process

Author

Devoivre, T. ; Papadas, C. ; Setton, M.

Author_Institution

Central R&D, ST Microelectron., Crolles, France

fYear

1999

fDate

14-16 June 1999

Firstpage

131

Lastpage

132

Abstract

This paper presents a 0.1 /spl mu/m Ta/sub 2/O/sub 5/ transistor, manufactured with an almost standard CMOS process. A complete set of electrical characteristics is presented and nonsilicided circuits have shown delay time as low as 40 ps/stage at the nominal conditions (i.e. 1.5 V). The device lifetime is above 10 years from both oxide breakdown and hot carrier endurance points of view.

Keywords

CMOS integrated circuits; MOSFET; delays; dielectric thin films; hot carriers; integrated circuit measurement; integrated circuit reliability; semiconductor device breakdown; tantalum compounds; 0.1 micron; 1.5 V; 10 yr; 40 ps; CMOS process; Ta/sub 2/O/sub 5/ transistor; delay time; device lifetime; electrical characteristics; hot carrier endurance; near-standard CMOS process; nonsilicided circuits; oxide breakdown; reliable Ta/sub 2/O/sub 5/ transistor; CMOS technology; Chemistry; Delay; Inverters; Leakage current; Leg; MOS devices; Manufacturing; Stress; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-930813-93-X

Type

conf

DOI

10.1109/VLSIT.1999.799378

Filename

799378

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3252043