Ultra-Thin Fully Depleted SOI Devices with Thin BOX, Ground Plane and Strained Liner Booster

The fully depleted (FD) SOI MOSFET is generally considered as one of the best candidates for next CMOS technology nodes. However, new technological boosters need to be introduced in the classical FD SOI process flow to reach the very aggressive I_on/I_off specifications predicted by the ITRS roadmap. The use of a thin buried oxide (BOX) on FD SOI is still a controversial subject, despite recent publications that have demonstrated its interest for improvement of short channel effect (SCE) control, especially with a ground plane (GP) integration (Tsuchiya et al.). In order to improve the device performances, a strained "contact etch stop layer" (CESL) technique has been successfully demonstrated to induce strain into the channel of bulk devices (Thompson et al., 2002) as well as in ultra-thin FD SOI devices (Singh et al., 2005 and Gallon et al., 2006). However, its compatibility with the specific technological features of FD SOI devices, such as silicon film thickness (T_S1) variations, BOX material and BOX thickness (T_BOX), raised source/drain architecture, has yet to be clarified. In this paper, we demonstrate, by electrical and mechanical simulations, the interest of thin BOX with GP, combined with a strained liner. These simulations have then been validated by measurements, showing excellent I_on/I_off pMOS performances