Optimization of Dual-ESL Stressor Geometry Effects for High Performance 65nm SOI Transistors

Author

Bo, Xiang-Zheng ; Grudowski, Paul ; Adams, Vance ; Loiko, Konstantin ; Tekleab, Daniel ; Filipiak, Stan ; Hackenberg, John ; Kolagunta, Venkat ; Foisy, Mark ; Lin, Li-Te ; Fung, K.H. ; Wu, Chi-Hsi ; Tuan, Hsiao-Chin ; Cheek, Jon

Author_Institution

Austin Silicon Technol. Solutions, Freescale Semicond. Inc., Austin, TX

fYear

2006

fDate

2-5 Oct. 2006

Firstpage

19

Lastpage

20

Abstract

We report on the optimized transverse and lateral boundaries of dual etch stop layer (dESL) stressors in both PMOS and NMOS achieved in 65nm SOI transistors. We demonstrate that this gives an additional ~20% performance gain in ring oscillators. The optimization takes into account the 1-D and 2-D geometry effects, including poly-pitch, and is in good agreement with stress simulations

Keywords

MOSFET; nanoelectronics; optimisation; silicon-on-insulator; 65 nm; NMOS; PMOS; SOI transistor; Si; dual etch stop layer; poly-pitch; stress simulations; stressor geometry effect optimization; Added delay; Compressive stress; Conference proceedings; Etching; Geometry; MOS devices; Performance gain; Ring oscillators; Solid modeling; Tensile stress;

fLanguage

English

Publisher

ieee

Conference_Titel

International SOI Conference, 2006 IEEE

Conference_Location

Niagara Falls, NY

ISSN

1078-621X

Print_ISBN

1-4244-0289-1

Electronic_ISBN

1078-621X

Type

conf

DOI

10.1109/SOI.2006.284411

Filename

4062859