A genetic local search hybrid architecture for VLSI circuit partitioning

During the last decade, the complexity and size of circuits have been rapidly increasing, placing a stressing demand on industry for faster and more efficient CAD tools for VLSI design. One major problem is the computational requirements for optimizing the place and route operations of a VLSI circuit. Thus, this paper investigates the feasibility of using reconfigurable computing platforms to improve the performance of CAD optimization algorithms for the VLSI circuit partitioning problem. The proposed reconfigurable computing genetic algorithm architecture achieved a five times speedup over conventional software implementation while maintaining 88% solution quality. Furthermore, a reconfigurable computing based hybrid algorithm improved upon this solution while using a fraction of the execution time required by the conventional software based approaches.