Title :
Performance Enhancement via Laser Anneal-Based RS/D Reduction in PD/SOICMOS
Author :
Trivedi, V.P. ; Spencer, G.S. ; Grudowski, P. ; Liu, J. ; Sing, D. ; Choi, P. ; Parsons, S. ; Kolagunta, V. ; Cheek, J.
Author_Institution :
Austin Silicon Technol. Solutions, Freescale Semicond. Inc., Austin, TX
Abstract :
Extrinsic source/drain series resistance (RSD/) becomes a limiting factor as performance boosters, such as strain-Si and metal-gate/high-k gate stack that enhance the intrinsic MOSFET, are vigorously pursued and implemented in nanoscale CMOS (Ghani, et al., 2003). Non-melt laser spike anneal (LSA) (Feng et al., 2004) has been suggested (Shima, et al., 2004), (Fung et al., 2004) as a means to reduce RSD/. In this paper, we present, for the first time, application of LSA to 35nm gate length, high-performance PD/SOI CMOS with dual etch stop layer (dESL) stressors and NiSi (Grudowski et al., 2006), showing 10% (4%) nFET (pFET) on-state current (Ion) enhancement and non-self-heated Ion=1520/1160muA/mum (880/630muA/mum) at VDD=1.2V/1.0V
Keywords :
CMOS integrated circuits; laser beam annealing; nickel compounds; silicon-on-insulator; 1 V; 1.2 V; 35 nm; NiSi; PD/SOI CMOS; Si; dual etch stop layer stressors; intrinsic MOSFET; nFET; nonmelt laser spike annealing; pFET; silicon-on-insulator; source-drain series resistance; Annealing; CMOS process; Conference proceedings; Etching; High K dielectric materials; High-K gate dielectrics; Intrusion detection; MOSFET circuits; Silicon; Very large scale integration;
Conference_Titel :
International SOI Conference, 2006 IEEE
Conference_Location :
Niagara Falls, NY
Print_ISBN :
1-4244-0289-1
Electronic_ISBN :
1078-621X
DOI :
10.1109/SOI.2006.284412
