Title :
A FRAM technology using 1T1C and triple metal layers for high performance and high density FRAMs
Author :
Lee, S.Y. ; Jung, D.J. ; Song, Y.J. ; Koo, B.J. ; Park, S.O. ; Cho, H.J. ; Oh, S.J. ; Hwang, D.S. ; Lee, S.I. ; Lee, J.K. ; Park, Y.S. ; Jung, I.S. ; Kinam Kim
Author_Institution :
Samsung Electron. Co., Yongin-City, South Korea
Abstract :
Recently, ferroelectric random access memory has drawn a great deal of attention due to inherent properties such as nonvolatility, long retention time, high endurance, fast access time, small cell size compared to DRAM cell size in principle, and strong resistance to /spl alpha/-particle and cosmic ray irradiation. None of the available commercial memories meet all of the properties of the ferroelectric memory. Although ferroelectric memory has inherent good properties, full utilization of these properties has not yet been realized. Commercially available products are limited to low densities. The commercially available ferroelectric memory uses a 2T2C (two transistor-two capacitor) structure with single level metal instead of a 1T1C (one transistor-one capacitor) structure with multiple metal layers which is believed to be essential for mega-bit or giga-bit density memory. In this paper, an integration technology for high performance and high density FRAMs is developed using a 1T1C robust capacitor in a COB (capacitor over bit line) structure with triple metallization processes. The technology developed in this paper is evaluated with an experimental 4 Mb FRAM, which is the highest FRAM density developed to date.
Keywords :
capacitors; ferroelectric storage; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; integrated memory circuits; random-access storage; 1T1C robust capacitor; 1T1C structure; 1T1C/triple metal layer structure; 2T2C structure; 4 Mbit; COB structure; DRAM cell size; FRAM density; FRAM performance; FRAM technology; access time; alpha-particle irradiation resistance; capacitor over bit line structure; cell size; cosmic ray irradiation resistance; endurance; ferroelectric memory; ferroelectric random access memory; integration technology; memory density; multiple metal layers; nonvolatility; one transistor-one capacitor structure; retention time; single level metal; triple metallization processes; two transistor-two capacitor structure; Capacitors; Contact resistance; Ferroelectric films; Nonvolatile memory; Paper technology; Random access memory; Surface treatment; Temperature; Testing; Wet etching;
Conference_Titel :
VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-930813-93-X
DOI :
10.1109/VLSIT.1999.799383
