Title :
I/O Architecture For Improved ESD Protection In Deep Sub-Micron SOI Technologies
Author :
Mitra, S. ; Gauthier, R. ; Salman, A. ; Putnam, C. ; Beebe, S. ; Halbach, R. ; Seguin, C.
Author_Institution :
IBM Microelectron., Essex Junction, VT
Abstract :
In this paper, the I/O structure described is based on a state of the art 65nm SOI technology designed for SRAM and logic applications (Leobandung et al, 2005). It is a twin-well partially depleted SOI (PDSOI) CMOS technology with gate oxide thicknesses of 1.05nm (SG) and 2.35nm (DG)
Keywords :
CMOS integrated circuits; SRAM chips; electrostatic discharge; input-output programs; logic devices; nanotechnology; silicon-on-insulator; 1.05 nm; 2.35 nm; 65 nm; CMOS technology; I/O architecture; PDSOI; SRAM applications; Si; deep sub-micron SOI technologies; gate oxide; improved ESD protection; logic applications; partially depleted SOI; CMOS technology; Clamps; Diodes; Electrostatic discharge; FETs; Immune system; Protection; Robustness; Silicon on insulator technology; Voltage;
Conference_Titel :
International SOI Conference, 2006 IEEE
Conference_Location :
Niagara Falls, NY
Print_ISBN :
1-4244-0289-1
Electronic_ISBN :
1078-621X
DOI :
10.1109/SOI.2006.284421
