FPGA based hardware architectures for iterative algorithms implementations

The paper describes the FPGA technology together with its possibility to exploit spatial and temporal parallelism in order to implement hardware architectures for iterative algorithms. The development of hardware architecture using FPGA technology represents a reliable solution in case of various applications where fast processing in case of iterative algorithms it´s mandatory. Two applications are presented where the FPGA technology is used for processing. Thus, on one hand, automatic microarray grid alignment is performed using FPGA based hardware architecture, while on the other hand, an FPGA based LDPC decoder implementation is proposed in order to improve the decoder throughput compared to state of the art approaches.