FinFET SRAM with Enhanced Read / Write Margins

Author

Carlson, A. ; Guo, Z. ; Balasubramanian, S. ; Pang, L.T. ; Liu, T. J King ; Nikolic, B.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA

fYear

2006

fDate

2-5 Oct. 2006

Firstpage

105

Lastpage

106

Abstract

In this work, the impact of this pass-gate feedback (PGFB) technique on cell write-ability is examined, and gate workfunction (Phi_m) tuning for optimization of the trade-off with read margin is discussed. To further improve cell write-ability, the p-channel pull-up devices can also be operated in BG mode, with their back gates driven by a separate write word line. This pull-up write gating (PUWG) technique is effective for maintaining larger than 6 standard deviations yield down to 0.4V VDD without area penalty, making FinFET-based 6-T SRAM compelling for high-density memory applications

Keywords

MOSFET; SRAM chips; circuit tuning; semiconductor device models; BG mode; FinFET SRAM; PGFB; PUWG; gate workfunction tuning; high density memory applications; p-channel pull-up devices; pass gate feedback; pull-up write gating; read/write margins; Conference proceedings; Degradation; Electrodes; Feedback; FinFETs; MOSFETs; Noise reduction; Random access memory; Transistors; Yield estimation;

fLanguage

English

Publisher

ieee

Conference_Titel

International SOI Conference, 2006 IEEE

Conference_Location

Niagara Falls, NY

ISSN

1078-621X

Print_ISBN

1-4244-0289-1

Electronic_ISBN

1078-621X

Type

conf

DOI

10.1109/SOI.2006.284456

Filename

4062904