DocumentCode
3253001
Title
Soft Error Performance of Z-RAM Floating Body Memory
Author
Fisch, David ; Beffa, Ray ; Bassin, Cedric
Author_Institution
Innovative Silicon Inc., Lausanne
fYear
2006
fDate
2-5 Oct. 2006
Firstpage
111
Lastpage
112
Abstract
The zero-capacitor (Z-RAMreg) floating body memory is a dynamic memory built on an SOI substrate. It differs from a DRAM cell in that it does not rely on an external capacitor to store charge and reading is done by sensing cell current. The Z-RAM memory cell stores charge in its floating body and uses this charge to alter the threshold voltage and gain of the cell transistor. The advantages of the Z-RAM cell are numerous and include a smaller cell size, lithographic friendly processing, fast access time, and no additional processing steps for use as an embedded memory (Okhonin et al., 2001). However, there is little published data on the soft error rates (SER) of this type of memory. This paper summarizes the results of accelerated alpha particle testing conducted on four, 1 Mbit Z-RAM test vehicles. As expected from the nature of the Z-RAM operation and its small cell size, its SER was observed to be significantly better than SRAM and comparable to the SER performance of embedded DRAM
Keywords
random-access storage; transistors; SOI substrate; Z-RAM floating body memory; alpha particle testing; cell current; dynamic memory; soft error performance; zero-capacitor; Alpha particles; Capacitors; Conference proceedings; Life estimation; Random access memory; Silicon; Single event upset; Testing; Vehicle dynamics; Vehicles;
fLanguage
English
Publisher
ieee
Conference_Titel
International SOI Conference, 2006 IEEE
Conference_Location
Niagara Falls, NY
ISSN
1078-621X
Print_ISBN
1-4244-0289-1
Electronic_ISBN
1078-621X
Type
conf
DOI
10.1109/SOI.2006.284459
Filename
4062907
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