DocumentCode
3253165
Title
DTMOS Low Noise Amplifier Design in Partially Depleted SOI CMOS Technology
Author
El Kaamouchi, M. ; Moussa, M. Si ; Raskin, J.P. ; Vanhoenacker-Janvier, D.
Author_Institution
Univ. Catholique de Louvain, Louvain-la-Neuve
fYear
2006
fDate
2-5 Oct. 2006
Firstpage
127
Lastpage
128
Abstract
This paper reviews and analyzes a low-noise amplifier (LNA) for low-power applications using a cascode inductive source degeneration topology, with a dynamic threshold MOSFET (DTMOS) transistor in 130 nm CMOS SOI technology. Thanks to the introduction of dynamic threshold-voltage MOSFET (DTMOS), the measurement of the LNA shows 13 dB gain and -30 dB reflection input, while dissipating 6 mW under 1.2 V supply
Keywords
CMOS analogue integrated circuits; MOSFET; low noise amplifiers; low-power electronics; silicon-on-insulator; 1.2 V; 13 dB; 130 nm; 6 mW; cascode inductive source degeneration topology; dynamic threshold MOSFET; low noise amplifier design; low-power application; partially depleted SOI CMOS technology; CMOS technology; Capacitance; Energy consumption; Low voltage; Low-noise amplifiers; MOS devices; MOSFET circuits; Silicon on insulator technology; Threshold voltage; Transconductance;
fLanguage
English
Publisher
ieee
Conference_Titel
International SOI Conference, 2006 IEEE
Conference_Location
Niagara Falls, NY
ISSN
1078-621X
Print_ISBN
1-4244-0289-1
Electronic_ISBN
1078-621X
Type
conf
DOI
10.1109/SOI.2006.284468
Filename
4062916
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