DocumentCode
3253584
Title
A 50 nm vertical Si0.70Ge0.30/Si0.85 Ge0.15 pMOSFET with an oxide/nitride gate dielectric
Author
Verheyen, P. ; Collaert, N. ; Caymax, M. ; Loo, R. ; Van Rossum, M. ; De Meyer, K.
Author_Institution
IMEC, Leuven, Belgium
fYear
2001
fDate
2001
Firstpage
15
Lastpage
18
Abstract
Vertical Reduced Pressure Chemical Vapour Deposition (RP-CVD) grown heterojunction pMOS transistors with a Si0.70Ge0.30/Si0.85Ge0.15 source stack have been fabricated with channel lengths down to 50 nm on a strain relaxed Si0.85Ge0.15 buffer layer. This paper reports on the viability of this source stack to suppress short channel effects in this channel length region. This is done by comparing the electrical characteristics of vertical Si0.85Ge0.15 homojunction transistors, and vertical Si0.70Ge0.30/Si0.85Ge0.15 heterojunction transistors, with channel lengths of 90 nm and 50 nm
Keywords
CVD coatings; Ge-Si alloys; MOSFET; semiconductor materials; 50 nm; Si0.70Ge0.30-Si0.85Ge0.15 ; Si0.70Ge0.30/Si0.85Ge0.15 vertical pMOSFET; buffer layer; channel length; electrical characteristics; heterojunction transistor; homojunction transistor; oxide/nitride gate dielectric; reduced pressure chemical vapour deposition; short channel effect; source stack; strain relaxation; Conductivity; Doping; Electric variables; Etching; Heterojunctions; Leakage current; MOSFET circuits; Silicidation; Silicides; Transconductance;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, Systems, and Applications, 2001. Proceedings of Technical Papers. 2001 International Symposium on
Conference_Location
Hsinchu
ISSN
1524-766X
Print_ISBN
0-7803-6412-0
Type
conf
DOI
10.1109/VTSA.2001.934470
Filename
934470
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