Mixed abstraction execution for the SoftSONIC virtual hardware platform

Author

Rissa, Tero ; Cheung, Peter Y K ; Luk, Wayne

Author_Institution

Dept. of Comput., Imperial Coll., London

fYear

2005

fDate

7-10 Aug. 2005

Firstpage

976

Abstract

This paper presents a systematic approach for mixed abstraction execution in the SoftSONIC virtual hardware platform. In mixed abstraction execution different levels of abstraction, for example clockless coarse granularity transaction level modelling (TLM) and clocked register transfer level (RTL) models can be co-simulated. When combining 10 Hz to 1 kHz-range RTL model of component under development with 100 kHz to 10 MHz-range TLM model of rest of the system, the full system simulates close to the speed of one RTL component alone. By verifying the components in full system simulation, error-prone and tedious per-component testbench generation can be avoided. Mixed abstraction execution also gives the possibility of gradual refinement and parallel development and verification of system components. These aspects can reduce the overall design time, as we show in this paper with the development of a real-time JPEG 2000 hardware encoder

Keywords

formal verification; hardware description languages; high level synthesis; image coding; 0.01 to 1.0 kHz; 0.1 to 10 MHz; JPEG 2000 hardware encoder; SoftSONIC virtual hardware; VHDL simulator; gradual refinement; granularity transaction level modeling; mixed abstraction execution; parallel development; register transfer level; system verification; Algorithm design and analysis; Clocks; Computational modeling; Digital circuits; Educational institutions; Hardware design languages; Mathematical model; Protocols; System testing; Virtual prototyping;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. 48th Midwest Symposium on

Conference_Location

Covington, KY

Print_ISBN

0-7803-9197-7

Type

conf

DOI

10.1109/MWSCAS.2005.1594266

Filename

1594266