Design of k-WTA/Sorting network using maskable WTA/MAX circuit

Author

Lin, Chi Sheng ; Ou, Shin Hong ; Bin-Da Liu

Author_Institution

Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

fYear

2001

fDate

2001

Firstpage

69

Lastpage

72

Abstract

This paper presents a novel circuit for the k-WTA/Sorting network that processes eight 8-bit patterns. This design is based on a maskable WTA/MAX circuit which generates maximum value and winner with maskable skill. It can obtain the whole system functions: WTA/MAX/k-WTA/Sorter without adding any extra components. The proposed hardware architecture features layout regularity and interconnection compactness, thus it can be exploited to obtain a small and efficient hardware implementation. The chip was fabricated with the TSMC 0.35□m SPQM CMOS process. Experimental results indicate this chip can work up to 66 MHz with power consumption less than 10 mW at 3.3 V supply voltage. This design is suitable for VLSI implementation. It can also be applied well when being embedded in digital signal processors

Keywords

CMOS digital integrated circuits; VLSI; digital signal processing chips; neural chips; sorting; 10 mW; 3.3 V; 66 MHz; 8 bit; SPQM CMOS process; TSMC; VLSI implementation; interconnection compactness; k-WTA/Sorting network; layout regularity; maskable WTA/MAX circuit; maskable skill; power consumption; whole system functions; CMOS process; Digital signal processors; Electronic mail; Energy consumption; Hardware; Integrated circuit interconnections; Power system interconnection; Sorting; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 2001. Proceedings of Technical Papers. 2001 International Symposium on

Conference_Location

Hsinchu

ISSN

1524-766X

Print_ISBN

0-7803-6412-0

Type

conf

DOI

10.1109/VTSA.2001.934485

Filename

934485