Implementing parallel algorithms on an FPGA directly from multithreaded Java using flowpaths

The performance of software executed on a microprocessor is adversely affected by the basic fetch execute cycle. A further performance penalty results from the load-execute-store paradigm associated with the use of local variables in most high level languages. Implementing the software algorithm directly in hardware such as on an FPGA can alleviate these performance penalties. Such implementations are normally developed in a hardware description language such as VHDL or Verilog. More recently, several methods for using C as a hardware description language and for compiling C programs to hardware have been researched with challenges in multithreading. Previous work shows how a new systems architecture for FPGAs, called flowpaths, can implement Java byte codes directly in an FPGA without the need for a microprocessor core. Results show that flowpaths perform within a factor of 2 of a minimal hand-crafted direct hardware implementation and orders of magnitude better than compiling the program to a microprocessor. This paper describes a method to extend the flowpath architecture to generate hardware directly from Java byte codes representing Java threads. This hardware executes multiple tasks in parallel supporting both synchronized and unsynchronized shared memory access. A producer/consumer example is implemented on a Xilinx Spartan IIE FPGA