Title :
Array transistor design challenges in trench capacitor DRAM technology
Author :
Li, Yujun ; Sim, Jai-Hoon ; Mandelman, Jack ; McStay, Kevin ; Ye, Qiuyi ; Bronner, Gary
Abstract :
BuriEd Strap Trench (BEST) array cell design has been extended for more than 4 generations. However, significant scaling challenges in planar trench DRAM technology will be encountered below the 0.1 μm generation. In this paper, we review the key factors that limit the scaling of the BEST array cell, further analyze the scaling challenges considering design for manufacturability, and finally discuss other design and/or technology innovations including the vertical array transistor to overcome scaling limitations
Keywords :
DRAM chips; capacitors; design for manufacture; 0.1 micron; BEST array cell; buried strap trench array cell; design for manufacturability; device scaling; planar trench capacitor DRAM technology; vertical array transistor; Capacitors; Doping; Isolation technology; Leakage current; Pulp manufacturing; Random access memory; Size control; Technological innovation; Threshold voltage; Voltage control;
Conference_Titel :
VLSI Technology, Systems, and Applications, 2001. Proceedings of Technical Papers. 2001 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
0-7803-6412-0
DOI :
10.1109/VTSA.2001.934489
