Performance analysis of single stage interconnection networks

Author

Burke, J. Richard ; Chen, Chienhua ; Lee, Tsung-Ying ; Agrawal, Dharma P.

Author_Institution

Semicond. Res. Corp., Research Triangle Park, NC, USA

fYear

1989

fDate

8-12 May 1989

Firstpage

31138

Lastpage

31868

Abstract

Single-stage interconnection networks (SSINs) have only one stage of switches and use recirculation through processors to provide the desired source-destination permutations. The authors describe an analytical probability model and simulation of SSINs using 2×2 switches. Four SSINs with different network sizes and loading and routing strategies are considered. Two possible cases of processors with and without buffers and three different routing strategies are applied in resolving conflicts. The simulation results show a close agreement to the analytical model

Keywords

multiprocessor interconnection networks; simulation; analytical model; analytical probability model; loading; performance analysis; recirculation; routing strategies; simulation; single stage interconnection networks; source-destination permutations; switches; Analytical models; Costs; Hardware; Military computing; Multiprocessor interconnection networks; Performance analysis; Routing; Switches; Topology; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

CompEuro '89., 'VLSI and Computer Peripherals. VLSI and Microelectronic Applications in Intelligent Peripherals and their Interconnection Networks', Proceedings.

Conference_Location

Hamburg

Print_ISBN

0-8186-1940-6

Type

conf

DOI

10.1109/CMPEUR.1989.93449

Filename

93449