DocumentCode
3253995
Title
Low temperature capacitor technology for embedded DRAM
Author
Lo, C.G. ; Yu, C.H. ; Chien, Wei-Ting Kary ; Huang, Charles H J
Author_Institution
Taiwan Semicond. Manuf. Co. Ltd., Hsinchu, Taiwan
fYear
2001
fDate
2001
Firstpage
105
Lastpage
108
Abstract
The experiments show that in the application of embedded DRAM, any post salicide process with temperature higher than 750°C would degrade the electrical performance of salicide, especially the P+ poly Rs. The novel capacitor dielectric stack film (nitride/capping HTO) is proved acceptable in view of leakage current density, Vbd and TDDB reliability below 700°C
Keywords
DRAM chips; capacitors; current density; dielectric thin films; integrated circuit reliability; leakage currents; 700 to 800 degC; TDDB reliability; capacitor dielectric stack film; electrical performance; embedded DRAM; leakage current density; low temperature capacitor technology; nitride/capping HTO; post salicide process; Annealing; Capacitors; Degradation; Electrodes; Furnaces; Leakage current; Logic; Oxidation; Random access memory; Temperature;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, Systems, and Applications, 2001. Proceedings of Technical Papers. 2001 International Symposium on
Conference_Location
Hsinchu
ISSN
1524-766X
Print_ISBN
0-7803-6412-0
Type
conf
DOI
10.1109/VTSA.2001.934494
Filename
934494
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