A new rail-to-rail readout circuit of CMOS image sensor for low power applications

In order to enhance the performance of CMOS image sensor under lower supply voltage, a new rail-to-rail pixel readout architecture is proposed in this paper. Due to the new readout circuit, the enough input voltage swing under low supply voltage is achieved and guaranteed for correct successive signal processing. As a consequence, the ability of working under lower voltage using the same process is greatly improved. The layout size of each pixel is 17mumtimes11.55mum. The design of a 64times64 bits CMOS image sensor circuit has been completed. The proposed CMOS image sensor can extend its operating voltage from 3.3V even down to 1.8V for a 0.35mum process. The total power dissipation is 0.528mW at 3.3V supply and down to 0.102mW at 1.8V