A cost effective binary FSK demodulator for low-IF radios

Author

Huang, Kuang-Hu ; Wang, Chorng-Kuang

Author_Institution

SOC Technol. Center, Ind. Technol. Res. Inst., Hsinchu, Taiwan

fYear

2001

fDate

2001

Firstpage

133

Lastpage

136

Abstract

This paper presents a design of low-cost continuous-phase binary frequency-shift keying (CP-BFSK) demodulator. The proposed demodulator does not require a post-detection filter to suppress sum-frequency components, and hence is suitable for a low-IF receiver architecture. Applied to a Bluetooth receiver with 500 kHz low-IF frequency, the demodulator reaches 10^-3 BER for 16.5 dB SNR and 1 Mbps data-rate. Small modulation indices between 0.28 to 0.35 are demonstrated. Using a 0.25-μm mixed-signal CMOS process, the demodulator occupies an active area of 0.22 mm². The power consumption is 5 mW from a 2.5 V single supply

Keywords

CMOS integrated circuits; VLSI; demodulators; digital radio; frequency shift keying; low-power electronics; mixed analogue-digital integrated circuits; 0.25 micron; 1 Mbit/s; 16.5 dB; 2.5 V; 5 mW; 500 kHz; ASIC; BER; Bluetooth receiver; binary FSK demodulator; binary frequency-shift keying; bit error rate; continuous-phase binary BFSK demodulator; cost effective demodulator; low-IF radios; low-IF receiver architecture; mixed-signal CMOS process; modulation indices; Bit error rate; Bluetooth; Costs; Delay; Demodulation; Detectors; Filtering; Filters; Frequency shift keying; Phase detection;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 2001. Proceedings of Technical Papers. 2001 International Symposium on

Conference_Location

Hsinchu

ISSN

1524-766X

Print_ISBN

0-7803-6412-0

Type

conf

DOI

10.1109/VTSA.2001.934501

Filename

934501