Title :
Tailoring logic CMOS for RF applications
Author :
Burghartz, Joachim N.
Author_Institution :
DIMES, Delft Univ. of Technol., Netherlands
Abstract :
The radio-frequency (RF) potential of logic CMOS is assessed in this paper. Steps towards an optimum RF performance are explained. Devices are optimized for the frequency responses (fT and f max), the minimum noise figure (Fmin), and the 1/f-noise based on device layout, bias conditions, and type of gate dielectric. Those steps are verified through a detailed study of IBM´s 0.18 μm CMOS logic technology. The identification of high RF performance of logic CMOS technology points out the advantage over dedicated RF CMOS technology
Keywords :
1/f noise; CMOS logic circuits; UHF integrated circuits; frequency response; integrated circuit noise; 0.18 micron; 1/f noise; CMOS logic; RF applications; bias conditions; device layout; frequency responses; gate dielectric; minimum noise figure; optimum RF performance; CMOS logic circuits; CMOS technology; Cutoff frequency; Equations; Logic devices; MOS devices; MOSFETs; Noise figure; Radio frequency; Roentgenium;
Conference_Titel :
VLSI Technology, Systems, and Applications, 2001. Proceedings of Technical Papers. 2001 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
0-7803-6412-0
DOI :
10.1109/VTSA.2001.934505
