Title :
A high performance CMOS device with inverter delay 13 ps at 1.2 V power supply
Author :
Chen, T.P. ; Biesemans, S. ; Cheng, S.M. ; Hong, Jerry ; Huang, Y.S. ; Cheng, Y.C. ; Holihan, K. ; Han, L.K. ; Schafbuer, T. ; Wann, C. ; Chen, J.K.
Abstract :
A gate delay 13 ps operating at 1.2 V has been developed for 0.13 μm CMOS logic technology application. In this work, the Leff of device is 0.08 um and the inversion oxide thickness is 3.2 nm. NMOS and PMOS transistor drive currents are 630 uA/um and 270 uA/um respectively at Ioff=4 nA/um. The Vt,sat rolloff from the nominal gate length to the worst gate length is about 50 mV for NMOS and 30 mV for PMOS
Keywords :
CMOS logic circuits; delays; inversion layers; logic gates; 0.13 micron; 1.2 V; 13 ps; 3.2 nm; 30 mV; 50 mV; CMOS logic technology; gate delay; gate length; inversion oxide thickness; inverter delay; transistor drive currents; CMOS logic circuits; CMOS technology; Capacitance; Delay; Implants; Inverters; Logic devices; MOS devices; Microelectronics; Power supplies;
Conference_Titel :
VLSI Technology, Systems, and Applications, 2001. Proceedings of Technical Papers. 2001 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
0-7803-6412-0
DOI :
10.1109/VTSA.2001.934509
