Multi-channel multi-point distribution service system transceiver implementation

Author

Dinh, Anh ; Bolton, R.J. ; Mason, Ralph ; Palmer, Ron

Author_Institution

TR Labs., Regina Univ., Sask., Canada

fYear

1999

fDate

1999

Firstpage

242

Lastpage

245

Abstract

This paper presents the hardware implementation of a high-speed transceiver to be used in a multi-channel multi-point distribution system (MMDS). Based on standards specifications, various building blocks are implemented using FPGA prototypes. It has been found that data integrity protection is expensive to implement, namely the forward error correction scheme in the transceiver. This includes Reed-Solomon codec and byte interleaving to correct both random and burst errors causing by the channel. Results show a data rate of 80 Mbit/s can be achieved using FPGA prototypes. Higher data rates are expected when final ASICs are developed

Keywords

Reed-Solomon codes; application specific integrated circuits; codecs; data communication equipment; digital radio; field programmable gate arrays; forward error correction; quadrature amplitude modulation; transceivers; 80 Mbit/s; ASIC; FPGA prototypes; MMDS; QAM; Reed-Solomon codec; burst errors correction; byte interleaving; data integrity protection; forward error correction; hardware implementation; high-speed transceiver; multi-channel multi-point distribution service; random errors correction; Codecs; Error correction codes; Field programmable gate arrays; Forward error correction; Hardware; Interleaved codes; Protection; Prototypes; Reed-Solomon codes; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Computers and Signal Processing, 1999 IEEE Pacific Rim Conference on

Conference_Location

Victoria, BC

Print_ISBN

0-7803-5582-2

Type

conf

DOI

10.1109/PACRIM.1999.799522

Filename

799522