DocumentCode
3254711
Title
Probabilistic IP verification
Author
Drechsler, Rolf ; Becker, Bernd
Author_Institution
Inst. of Comput Sci., Albert-Ludwigs-Univ., Freiburg, Germany
fYear
1999
fDate
1999
Firstpage
305
Lastpage
308
Abstract
Modern VLSI CAD makes intensively use of core based design and integration of Intellectual Property (IP) to handle the IC design complexity. Several methods for IP integration in today´s design flow have been proposed. In this paper we present a new model for verification of designs using IP. We make use of probabilistic algorithms to verify a circuit. Our model allows the IP owners and creators to keep all detailed information about the design, while the designer can probabilistically verify his design
Keywords
VLSI; circuit CAD; formal verification; industrial property; integrated circuit design; IC design; VLSI CAD; circuit verification; intellectual property; probabilistic algorithm; Adders; Circuits; Computer science; Costs; Design automation; Design engineering; Intellectual property; Microprocessors; Software design; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications, Computers and Signal Processing, 1999 IEEE Pacific Rim Conference on
Conference_Location
Victoria, BC
Print_ISBN
0-7803-5582-2
Type
conf
DOI
10.1109/PACRIM.1999.799537
Filename
799537
Link To Document