Reconfigurable state-machine oriented flow-based router design

Traditional Internet protocol (IP) address lookup is one of the major performance bottlenecks in high-end routers. Prior art has investigated into architectures for flow-based IP address lookup engines based on programmable finite state machines (FSMs), which when implemented in a regular structured hardware engine, has led to the classical update problem in improving the reprogramming time of each machine and effective scheduling of the individual machines in the context of router database update. This paper describes a distributed co-evolving architecture that looks into the issue of an optimal hardware-software partition for flow-based routing from the viewpoint of memory and resource optimizations