Title :
A 24-mW 0.02-mm2 1.5-GHz DLL-Based Frequency Multiplier in 130-nm CMOS
Author :
Mesgarzadeh, Behzad ; Alvandpour, Atila
Author_Institution :
Div. of Electron. Devices, Linkoping Univ., Linkoping
Abstract :
This paper presents a low-power small-area DLL-based frequency multiplier. Instead of using edge combiner-based clock synthesis scheme, the proposed frequency multiplier utilizes a ring oscillator, which is controlled by a DLL. An injection-locked slave ring oscillator is used for jitter suppression. The implementation of the proposed structure in 130-nm CMOS occupies an area of 0.02 mm2. It operates in the frequency range of 100 MHz to 1.5 GHz while consuming 24-mW power from a 1.2-V supply at 1.5 GHz. The measured output phase noise at 1.5 GHz is -100.1 dBc/Hz at a 4-MHz frequency offset.
Keywords :
CMOS integrated circuits; delay lock loops; frequency multipliers; injection locked oscillators; integrated circuit noise; jitter; phase noise; CMOS; DLL-based frequency multiplier; delay-locked loop; frequency 100 MHz to 1.5 GHz; injection-locked slave ring oscillator; jitter suppression; output phase noise; power 24 mW; size 130 nm; voltage 1.2 V; Circuit stability; Clocks; Energy consumption; Feedback loop; Frequency conversion; Phase frequency detector; Phase locked loops; Ring oscillators; Transfer functions; Voltage-controlled oscillators;
Conference_Titel :
SOC Conference, 2006 IEEE International
Conference_Location :
Taipei
Print_ISBN :
0-7803-9781-9
Electronic_ISBN :
0-7803-9782-7
DOI :
10.1109/SOCC.2006.283893
