Title :
A Mimo Receiver SOC for CDMA Applications
Author :
Chen, Tongtong ; Yu, Zhengtao ; Peng, Yuantao ; Zhang, Yanbin ; Dai, Huaiyu ; Liu, Xun
Author_Institution :
Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC
Abstract :
In this paper, we present a systems-on-chip (SoC) design for the 3G code division multiple access (CDMA) receiver using the multiple-input multiple-output (MIMO) technique. Our chip integrates the entire digital signal processing part of the receiver. Furthermore, the proposed design can be reconfigured in real-time to handle different modulation schemes based on the signal-to-noise ratio, resulting in the highly efficient use of spectrum and energy. Designed using a 0.18 mum standard cell library, our chip has a core area of 20 mm2 and achieves a maximal throughput of 5 Mbps in simulation with 610 mW power dissipation.
Keywords :
3G mobile communication; CMOS integrated circuits; MIMO communication; channel capacity; code division multiple access; integrated circuit design; quadrature amplitude modulation; quadrature phase shift keying; radio receivers; reconfigurable architectures; system-on-chip; wireless channels; 3G code division multiple access receiver; CDMA applications; MIMO receiver SoC; QAM; QPSK modulations; bit rate 5 Gbit/s; digital signal processing; maximum likelihood MIMO detection; modulation schemes; multiple-input multiple-output technique; power 610 mW; power dissipation; real-time reconfiguration; signal equalization; signal-to-noise ratio; size 0.18 mum; standard cell library; systems-on-chip design; turbo decoding; wireless channel capacity; CMOS technology; Flash memory; MIMO; Maximum likelihood decoding; Maximum likelihood detection; Multiaccess communication; Power dissipation; Receiving antennas; Transmitters; Transmitting antennas;
Conference_Titel :
SOC Conference, 2006 IEEE International
Conference_Location :
Taipei
Print_ISBN :
0-7803-9781-9
Electronic_ISBN :
0-7803-9782-7
DOI :
10.1109/SOCC.2006.283897
