Effects of Interconnect Process Variations on Signal Integrity

With the development of new sub micron very large scale integration (VLSI) technologies the importance of interconnect parasitics on delay and noise has been in an ever increasing trend [1]. Consequently, the variations in interconnect parameters have a larger impact on final timing and functional yield of the product. Therefore, it is necessary to handle process variations as accurately as possible in layout parasitic extraction (LPE), static timing (ST) and signal integrity (SI) in deep sub-micron designs. In this paper we analyze the sources of process variation that induce interconnect parasitic variations. We present the relatively important ones through the usage of a response surface model (RSM). It was found that, in addition to metal thickness and width variation, damaged dielectric regions on the side of the metal lines are important contributions to cross-talk. We demonstrate the importance of accounting for the correlation between parameters for a given interconnect line such as interconnect line resistance and thickness. Finally we present a Monte Carlo (MC) methodology based on the RSM which can significantly reduce separation of corners and lead to tighter product specs and hence smaller die area and lower power.