Title :
A Low-swing Signaling Circuit Technique for 65nm On-chip Interconnects
Author :
Venkatraman, Vishak ; Anders, Mark ; Kaul, Himanshu ; Burleson, Wayne ; Krishnamurthy, Ram
Author_Institution :
Intel Labs., Intel Corp., Hillsboro, OR
Abstract :
This paper describes a low-swing on-chip interconnect signaling technique. A simple receiver circuit enables significant total energy and delay reduction compared to conventional repeaters over intermediate and global interconnects. A 5 mm minimum pitch global interconnect in 65nm CMOS technology using 1.1V supply exhibits a reduction of 56% in total energy, 21% in delay, and 86% in area.
Keywords :
CMOS integrated circuits; integrated circuit interconnections; system-on-chip; CMOS technology; delay reduction; low swing signaling circuit; on chip interconnects; receiver circuit; size 65 nm; CMOS technology; Capacitance; Crosstalk; Delay; Integrated circuit interconnections; Inverters; MOS devices; Repeaters; Voltage; Wire;
Conference_Titel :
SOC Conference, 2006 IEEE International
Conference_Location :
Taipei
Print_ISBN :
0-7803-9781-9
Electronic_ISBN :
0-7803-9782-7
DOI :
10.1109/SOCC.2006.283900
