Title :
A VHDL library for current-mode CMOS multiple-valued logic
Author :
Teng, D.H.Y. ; Bolton, R.J.
Author_Institution :
Dept. of Electr. Eng., Saskatchewan Univ., Saskatoon, Sask.
Abstract :
This paper discusses the design and use of a VHDL library for current-mode CMOS multiple-valued logic (MVL) simulation. The library has basic MVL entities, complex MVL entities as well as standard binary logic gates. A bus resolution function working cooperatively with the basic MVL entities allows MVL logic levels (currents) in individual connections to be output. Design examples of a quaternary full adder and one segment of a match filter are presented along with both VHDL and circuit simulation results
Keywords :
CMOS logic circuits; adders; circuit simulation; current-mode logic; hardware description languages; logic gates; logic simulation; multivalued logic circuits; software libraries; MVL entities; VHDL library; bus resolution function; circuit simulation results; current-mode CMOS multiple-valued logic; match filter; quaternary full adder; standard binary logic gates; Adders; CMOS logic circuits; Circuit simulation; Hardware design languages; Instruments; Libraries; Logic design; Logic gates; Mirrors; Switches;
Conference_Titel :
Communications, Computers and Signal Processing, 1999 IEEE Pacific Rim Conference on
Conference_Location :
Victoria, BC
Print_ISBN :
0-7803-5582-2
DOI :
10.1109/PACRIM.1999.799568
