A low power analog feed forward equalizer for gigabit Ethernet

An analog feed forward error equalizer (AFFE) is described that cancels precursor inter symbol interferences (ISI) in the front end of Gigabit Ethernet on twisted pair interfaces. Forward equalizing in analog domain not only reduces the complexity and area of digital forward equalizer, but also leads to lower power consumption and higher speed. The proposed equalizer based on five taps, discrete time filtering, designed in a 0.18μm CMOS technology. The design operates at 125MHz while consuming 57mW from a 2.5V supply. The low power design is achieved by liner, low power transconductor used for each bit of FIR filter coefficients in analog multiplier. Moreover S/H power and speed requirements are relaxed by using a redundant S/H and an additional clocking phase.