IP protection for FPGA implementation of DSP algorithms

In this paper, a novel watermarking method is proposed to embed a watermark at layout level for FPGA implementation of DSP algorithms. In the proposed scheme, the watermark bits are embedded by taking advantage of location information of the FPGA cells that store the data of the DSP algorithms. The new method does not require modification of the design. It is also different from the methods using the unused look-up table (LUT) components or using auxiliary data within an FPGA design file. The simulation results show that the new proposal has advantages in terms of hardware and time overheads, and embedding and extraction costs, compared to the other recent similar proposals.