The high throughput bit plane decoder for JPEG2000 based on selective sample skipping algorithm

The JPEG2000 block decoder consists of the bit plane decoder (BPD) tightly coupled with the arithmetic decoder (AD). The BPD generates contexts which are used by the AD to decode sample bits from the compressed bit-stream. The context generation process depends on the decoded bits and thus the BPD has to stall in most cases before it can load a new stripe-column to process. In this paper we present a new selection based sample skipping strategy to restrict the dependence of context generation on decoded bits. This enables the BPD to generate 1 context/clock-cycle for non-empty stripe-columns without stalling to load a new stripe-column. Further we propose speculative technique to improve the operating frequency of our architecture at the expense of extra hardware. The proposed BPD is implemented on an Altera Stratix FPGA. The implementation results show that the proposed architectures yield 50.1-107.1% increase in throughput with only a 27-37% increase in the hardware cost.