Performance evaluation of parallel FIR filter optimizations in ASICs and FPGA

This paper addresses constant coefficients parallel FIR filter optimizations. The optimizations proposed use a combination of two approaches: the reduction of the coefficients to a limited number of power-of-two (PT) terms, where the maximum number of non-zero bits is set as a constraint, followed by common sub-expression elimination (CSE) among multipliers. Implementation results and the optimization effects in area, delay, and power for FPGAs and CMOS standard cells designs are presented. We show that it is possible to achieve area savings for both, ASIC or FPGAs implementation. Additional results for ASIC area are compared when timing constrained physical synthesis from a 0.35mum CMOS cell library is performed