Asynchronous pipelined MB-OFDM UWB transceiver on FPGA

The key requirement of 200 Mbps MB-OFDM UWB wireless system is that the OFDM block which is a 128 point FFT/IFFT processor has to operate at 528 MHz. The same way, a 64 state, rate-1/3 Viterbi decoder block is needed but this has to operate at 125 MHz. Novel schemes are essential for achieving these speeds on FPGAs. In this paper, novel schemes are proposed to meet the challenges of FPGA based OFDM and Viterbi decoder blocks to implement MB-OFDM UWB transceiver. The advantages of asynchronous pipelining techniques are high speed, low power consumption, absence of clock-skew problem, etc., In this paper, as an initiative work, FPGA based MB-OFDM UWB transceiver using asynchronous pipelining technique with proposed schemes is presented. Bundled-data protocol with four-phase is used for asynchronous implementation. The OFDM module is designed using Two-parallel data path Radix-2⁴ SDF FFT/IFFT with modified structure to obtain the required operating frequency of 528 MHz. A two-stage radix-4 Viterbi decoder with 2-pointer algorithm is proposed to reduce the memory requirement and latency of the previous implemented 3-pointer algorithm. LPM modules from ALTERA is also used to achieve the high speed requirement of MB-OFDM UWB system. The proposed asynchronously pipelined MB-OFDM UWB transceiver digital backend modules has been tested on ALTERA STRATIX III EP3SE110F780C2 FPGA by forming digital loop back and the results are compliance to the ECMA 368 standard. To the best of our knowledge, the proposed work is first of its kind.