STBus transaction level models using SystemC 2.0

SystemC 2.0 facilitates the development of transaction level models (TLM) that are models of the hardware system components at a high level of abstraction. System architects can quickly develop these models and be ready with an executable specification of the hardware blocks as soon as the initial functional specifications of the system are decided. In this paper, we present a SystemC 2.0 TLM of the STBus architecture developed by STMicroelectronics, oriented to SOC platform architectures, by focusing on the advantages and limits of this abstraction level. Then, we propose a solution to these limits.