VLSI implementation of discrete Mellin transform for real time scale analysis of images

The Mellin transform (MT) is a form of a signal representation similar to Fourier transform (FT) which has been widely used in signal processing owing to its distinct properties like scale invariance. In this work, a 2D form of MT which is termed as 2D discrete Mellin transform (DMT) is introduced. The paper also proposes an area efficient, power aware and multiplier less VLSI architecture for 2D DMT for real time applications and discusses 2D DMT implementation to identify scaled images and the amount of scaling involved. Previous implementations involve operations which are error prone and hard to realize on silicon. The proposed architecture overcome these limitations and has pipeline design to address the computational complexity. The critical path in the architecture is an adder and a multiplexer equivalent. The latency depends on the number and depth of CORDIC blocks and the image size. The validity of the algorithm is supported by Matlab simulations and FPGA synthesis results.