A switched-capacitor Hadamard filter bank in 0.35 /spl mu/m CMOS

Author

Brandão, Paulo Cesar Ramalho ; Petraglia, Antonio

Author_Institution

Dept. of Electr. Eng., COPPE - Rio de Janeiro Fed. Univ.

fYear

2005

fDate

7-10 Aug. 2005

Firstpage

1641

Abstract

This paper describes the design of filter banks that implement analog Hadamard transformers suitable to CMOS technology. A switched-capacitor (SC) topology is employed, including finite-gain and offset compensation techniques to allow the use of low-gain high-bandwidth amplifiers, thereby enabling signal processing by the filter bank at high data rates. The structure may be used as an analysis stage in what has been termed a hybrid filter bank, where post digital signal processing stage can be incorporated to improve A/D conversion accuracy and speed, or in digital communication systems to reduce transmission data rates. Design details, as well as simulation results for a 0.35 mum CMOS manufacturing process are presented, verifying the effectiveness of the proposed scheme

Keywords

CMOS digital integrated circuits; Hadamard transforms; analogue-digital conversion; digital signal processing chips; switched capacitor filters; 0.35 micron; A/D conversion accuracy; CMOS manufacturing process; Hadamard filter bank; SC topology; analog Hadamard transformer; digital communication system; digital signal processing stage; finite-gain compensation technique; high-bandwidth amplifier; hybrid filter bank; low-gain amplifier; offset compensation technique; switched-capacitor filter bank; CMOS process; CMOS technology; Digital communication; Digital signal processing; Filter bank; Manufacturing processes; Signal analysis; Signal processing; Topology; Transformers;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. 48th Midwest Symposium on

Conference_Location

Covington, KY

Print_ISBN

0-7803-9197-7

Type

conf

DOI

10.1109/MWSCAS.2005.1594432

Filename

1594432