Title :
Modeling and optimization of mixed logic circuits: the CMOS/CPL combination
Author :
Wan, Yuanzhong ; Shams, Maitham
Author_Institution :
Carleton Univ., Ottawa, Ont., Canada
Abstract :
Effective optimization methods aimed at achieving maximal speeds in single-technology logic circuits are widely available but systematic ways suitable for circuits involving mixtures of logic families are not. In this paper, the combination of standard CMOS with CPL is examined with an eye to finding the best structure and the best insertion points for CMOS buffers intended to improve a CPL chain´s propagation time and drive capability.
Keywords :
CMOS logic circuits; buffer circuits; circuit optimisation; delay circuits; integrated circuit design; integrated circuit modelling; logic design; CMOS buffers; CMOS-complementary pass transistor logic circuits; delay circuits; integrated circuit design; logic design; mixed logic circuit modeling; mixed logic circuit optimization; single technology logic circuits; CMOS digital integrated circuits; CMOS logic circuits; Capacitance; Delay; Inverters; Logic circuits; MOS devices; MOSFETs; Semiconductor device modeling; Voltage;
Conference_Titel :
Microelectronics, 2004. ICM 2004 Proceedings. The 16th International Conference on
Print_ISBN :
0-7803-8656-6
DOI :
10.1109/ICM.2004.1434603
