Improving response time of programmable logic controllers by use of a Boolean coprocessor

Programmable-logic controllers (PLCs) are widely used to control technical processes in the industrial environment. In the requirements for next-generation PLCs, their fast response to events from the controlled processes plays a central role. The author shows that the response time of a low-cost PLC can be shortened by at least a factor of ten by using a special Boolean coprocessor in conjunction with the PLC (micro-) processor. The speedup is achieved by two means: (1) an architecture of the Boolean coprocessor designed for very fast execution of instructions on bit data, and (2) parallel execution of bit- and word-instruction streams with an efficient synchronization mechanism between them. The Boolean coprocessor´s design is completed at the register transfer level. Simulation at the register transfer level and a gate-level simulation of the critical data path indicate an instruction-cycle time of less than 0.3 μs. The VLSI realization of the design requires a gate array of 4000 gates with a 2-kb fast on-chip RAM