Challenges and advances in electrical interconnect analysis

The authors review key issues regarding electrical interconnect analysis (EIA) for VLSI parasitic circuits. They give a general introduction to important aspects for technologies with a variety of performances and then review some issues relating to the state of the art for high-performance chips and packages. For high-performance technologies, the state-of-the-art tools leave a lot to be desired. The methods of choice for EIA are integral formulations like the method of moments or circuit-based techniques because the regions to be analyzed are usually open. Circuit based formulations like the rPEEC (retarded partial element equivalent circuit) approach are advantageous because they can be combined with other circuit models like transistors and because they can be used in the time and frequency domains. An example of a trace on a printed circuit board driven by a standard TTL 74F04 inverter chip is included