Title :
Test-set preserving logic transformations
Author :
Batek, Michael J. ; Hayes, John P.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
Abstract :
Logic transformations that preserve minimal or complete test sets of a combinational circuit are examined. Some basic transformation types are rigorously defined and characterized with respect to test-set preservation. The authors apply the transformations to adder design and show that any complete test set for a two-level adder is preserved on transformation to ripple-carry and carry-lookahead designs, thus verifying some recent simulation results
Keywords :
adders; combinatorial circuits; logic design; logic testing; adder; carry-lookahead designs; combinational circuit; complete test sets; ripple-carry; simulation; test set preserving logic transformations; test-set preservation; Adders; Circuit faults; Circuit simulation; Circuit synthesis; Circuit testing; Delay estimation; Electrical fault detection; Fault detection; Logic circuits; Logic testing;
Conference_Titel :
Design Automation Conference, 1992. Proceedings., 29th ACM/IEEE
Conference_Location :
Anaheim, CA
Print_ISBN :
0-8186-2822-7
DOI :
10.1109/DAC.1992.227760
